555 overcurrent latch
13 parts
A 4.7 Ω shunt sits between the raw 12 V rail and everything downstream — including the timer's own Vcc pin — so load current literally pulls the chip's supply down, while the pot divider hangs off the rail upstream of the shunt and holds the threshold pin at a fixed, measured 7.7277 V. At the 470 Ω working load the shunt carries a measured 25.279 mA and Vcc sits at 11.8812 V, comfortably above the setpoint; when a 47 Ω fault lands at 12 ms the current jumps to 252.975 mA, Vcc falls to 10.8110 V, and the threshold comparator wins — the output drops from 11.8812 V to 0 at a measured t = 12.0001 ms and the LED goes dark. It stays dark: the fault clears at 15 ms and the latch does not re-arm, which is exactly what a protection circuit should do. The timer is a behavioural macromodel — exact ⅓/⅔ comparators with no offset, no propagation delay, no RESET or CONTROL pin, no quiescent supply current, and an output branch referenced to its own ground pin, so the LED's measured 8.764 mA never flows through the shunt.
- V1 12V
- POT1 100kΩ·56%
- R1 25kΩ
- R2 10kΩ
- R3 10kΩ
- TDSW1 0s
- R4 4.7Ω
- T5551
- R5 470Ω
- TDSW2 12ms
- R6 47Ω
- LED1
- R7 1kΩ
