Half-bridge dead time
7 parts
A complementary PWM generator (20 kHz, 8 µs dead time) runs a transistor half-bridge into an L–R load. The high-side switch gets its gate through a floating driver whose return pin rides the switch node — that floating pair is the level shift; a ground-referenced gate cannot hold a gate voltage across a flying source — while the low-side transistor-plus-diode is driven directly. In every 8 µs gap where both commands are low the inductor current must keep flowing, so it drags the node a diode drop below ground and freewheels through the low-side antiparallel diode: measured −0.78 V. Labelled macromodels throughout: the dead time is the delayed-self-gating law OUT = raw(t)·raw(t−Td), non-overlapping by construction for any Td ≥ 0; the switches are gated real diode junctions with honest forward drops but no switching-loss physics; the driver is a behavioural level shifter.
- V1 12V
- PWMC1 20kHz·50%
- GDRV1
- TSW1 ≥4V
- TAD1 ≥4V
- L1 1mH
- R1 47Ω
