SR and D latches

by ourcircuits

6 parts

Level-sensitive memory in its two classic flavours — the sequential building blocks that are often locked behind a paywall elsewhere ship free here. The SR latch remembers which input pulsed last: 0.8 ms set pulses arrive every 4 ms with the reset train running exactly 2 ms behind, so Q rises on every S pulse and clears on every R. The D latch is transparent instead: while EN is high its Q chases the 900 Hz data line, and the instant EN falls it freezes whatever the data was doing.